The fabrication of a memory device typically requires a number of steps including lithography, deposition of various constituent materials, patterning, etching, etc. However, the continual reduction in the size of individual memory elements, and the continual increase in the density with which such memory elements are fabricated on memory devices, are challenging the limits of current lithography and patterning technology. For example, presently existing lithography and patterning technology is typically not well suited for forming features having a pitch less than about 32 nanometers. Accordingly, improved methods of patterning memory cells for use in memory devices are desirable. In particular, methods for forming memory elements having small pitch are desirable.
In previous 3D memory arrays, individual memory lines have been interleaved from drivers on two sides of the array. This provides a pitch relief of two to one at the edge of the array. Pitch doubling techniques are desirable for increasing the density of the array lines but a method is needed to interleave these lines in a manner that provides pitch relief in the support connection layout. With half pitch memory lines, using pitch double techniques shrinking to less than the minimum feature size of the lithography tools, more than 2 to 1 pitch relaxation may be required for connecting support circuits to these dense memory arrays. The size of the support circuit connections (e.g., zias) may not shrink as rapidly and may not benefit from pitch doubling techniques. Accordingly, improved methods of relaxing the pitch requirements for support circuit connections are desirable.